1. Technical Field
This disclosure pertains generally to filling through vias in support of integrated circuit interconnections, and more particularly to a using an inkjet printer for filling through vias within integrated circuits.
2. Discussion
Semiconductor packaging applications often require the integration of three-dimensional (stacked) packages toward increasing effective circuit functionality per area. Vias in these circuits, known as through-silicon-vias (TSVs) are widely recognized as one of many necessary building blocks for realizing this stacking capability. Although the concept of chip-stacking is known, TSV development is a nascent area of research with fully effective methods for filling TSVs not yet established.
TSVs are currently being fabricated using deep reactive ion etching (DRIE) or laser drilling on silicon-on-insulator (SOI) wafers and the via formation may occur before complementary metal-oxide semiconductor (CMOS) fabrication, between CMOS and back-end-of-line (BEOL) processing, after BEOL processing, or after die bonding. It will be noted that BEOL processing is the second portion of integrated circuit (IC) fabrication where the individual devices (transistors, capacitors, resistors, and so forth) are interconnected with wiring. Current approaches for filling these etched or drilled vias include copper electroplating, tungsten filling, and insulation of highly doped silicon. Potential alternatives can include varying the deposited material for electroplating or chemical vapor deposition (CVD) and the introduction of atomic layer deposition (ALD) for very small and high aspect ratio TSVs. Or if on-chip processing of TSVs is avoided altogether, then alternatives include use of silicon interposers and stacked wire bond devices provide potential alternatives.
There are drawbacks to each of these processes, many of the more practical of which are wafer-scale, blanket deposition, subtractive techniques which requires multiple processing steps in order to obtain an insulated, fully-filled via plug.
Therefore, a method is needed for performing rapid TSV filling and bumping with a die-scale to wafer-scale additive process which is tunable and that reduces material consumption.